Formal Engineering Research using Methods , Abstractions and Transformations Technical Report

Concurrent execution of multiple operations in a single clock cycle of a hardware design may increase its peak power which can lead to cooling, packaging and reliability issues. In this paper, we consider a model of computation based on high-level atomic transactions which has been shown to synthesize hardware designs comparable to hand-written Verilog in terms of area and latency. In hardware generated using such models, concurrent execution of maximal set of transactions in each clock cycle reduces the latency of the design at the cost of increase in its peak power. We propose a peak power reduction algorithm which targets the optimization of latency under a specified peak power constraint. We experimented with the proposed algorithm by implementing it in an academic version of Bluespec Compiler, a commercial highlevel synthesis tool, which uses a similar model of computation to generate efficient RTL code from atomic transactions. It is noteworthy that such atomic transactions based models can also be written in SystemC or any other highlevel hardware description language, with synthesis pragmas to denote atomic transactions boundaries. Our experiments show that the proposed algorithm can reduce the peak power of hardware designs (upto 20% reduction achieved) without too much sacrifice in their latency. We conclude that the proposed algorithm exploits the high abstraction level (above RTL) of atomic transactions to offer the benefits of easier power management and faster architectural exploration, thus increasing the overall productivity. Peak power and Latency Optimized Hardware Synthesis from Atomic Transactions based High-Level Model. Gaurav Singh Sandeep K. Shukla {gasingh, shukla}@vt.edu